View ADV7541BCBZ-2RL_7864551.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low power hdmi/dvi transmitter with de-interlacer and cec adv7541 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009-2010 analog devices, inc. all rights reserved. features general low power hdmi/dvi transmitter ideal for portable applications de-interlacer operates from 480i to 1080i with no external memory required cec controller and buffer reduces system overhead incorporates hdmi v.1.4 (x.v.color) technology compatible with dvi v.1.0 optional embedded hdcp keys to support hdcp 1.3 single 1.8 v supply video/audio inputs accept logic levels from 1.8 v to 3.3 v digital video 150 mhz operation supports all video and graphics resolutions from 480i to 1080p de-interlacer requires no external memory programmable 2-way color space converter supports rgb, ycbcr, and ddr supports itu656-based embedded syncs auto input video format timing detection (cea-861e) digital audio supports standard s/pdif for stereo lpcm or compressed audio up to 192 khz 2-channel uncompressed lpcm i 2 s audio up to 192 khz special features for easy system design on-chip mpu with i 2 c master to perform edid reading and hdcp operations; reports hdmi events through interrupts and registers 5 v tolerant i 2 c and hpd i/os, no extra device needed no audio master clock needed for supporting s/pdif and i 2 s 5 v generator for hot plug detect in portable applications applications cellular handsets digital video cameras digital still cameras personal media players gaming dvd players and recorders digital set-top boxes hdmi repeaters functional block diagram d[15:0] v syn c hsync de clk i 2 c slave sd a scl hdcp core hdcp and edid micro- controller i 2 c master in t hpd ddcscl tx0 tx1 tx2 txc ddcsda adv7541 tmds outputs s/pdif mclk* i 2 s lrclk *the sclk serves as mclk when configured with s/pdif. sclk* cecio cecclk cec controller buffer color space conversion sync adjustment and generation de-interlacer audio data capture video data capture register configuration logic hdcp keys 08241-001 figure 1. general description the adv7541 is a 150 mhz, high definition multimedia interface (hdmi) transmitter. it supports hdtv formats up to 1080p and computer graphic resolutions up to sxga at 75 hz. with the optional inclusion of embedded hdcp keys, the adv7541 allows the secure transmission of protected content, as specified by the hdcp 1.3 protocol. the adv7541 supports x.v.color? (gamut metadata) for a wider color gamut. the adv7541 supports both s/pdif and 2-channel i 2 s audio. its high fidelity, 2-channel i 2 s can transmit stereo at up to a 192 khz sampling rate. the s/pdif can carry stereo lpcm audio or compressed audio including dolby? digital and dts?. the adv7541 helps to reduce system design complexity and cost by incorporating such features as an i 2 c? master for edid reading and 5 v tolerance on i 2 c and hot plug? detect pins. fabricated in an advanced cmos process, the adv7541 is available in a space-saving, 49-ball wlcsp surface-mount package. this package is rohs compliant and specified to operate from ?25c to +85c.
adv7541 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical specifications ............................................................... 3 ? absolute maximum ratings ............................................................ 5 ? explanation of test levels ............................................................5 ? esd caution...................................................................................5 ? pin configuration and function descriptions ..............................6 ? applications information .................................................................8 ? design resources ..........................................................................8 ? outline dimensions ..........................................................................9 ? ordering guide .............................................................................9 ? revision history 6/10rev. 0 to rev. a updated to hdmi v.1.4 ................................................ throughout changes to ordering guide ............................................................ 9 7/09revision 0: initial version
adv7541 rev. a | page 3 of 12 specifications electrical specifications avdd = dvdd = 1.8 v. table 1. parameter temp test level 1 min typ max unit test conditions/ comments digital inputs data clock clk to input jitter 25c iv 2 ns data inputs (video and audio) input voltage, high v ih full vi 1.4 3.5 v input voltage, low v il full vi ?0.3 +0.7 v input capacitance 25c viii 1.0 1.5 pf i 2 c lines (ddcsda, ddcscl, sda, scl) input voltage, high v ih full vi 1.4 5.0 v input voltage, low v il full vi ?0.3 +0.8 v cecio and cecclk input voltage, high v ih full vi 1.4 3.5 v input voltage, low v il full vi ?0.3 +0.7 v digital outputs output voltage, high v oh full vi v dd ? 0.1 v output voltage, low v ol full vi 0.4 v thermal characteristics thermal resistance junction-to-case jc full v 20 c/w junction-to-ambient ja full v 43 c/w ambient temperature t a full v 0 25 85 c dc specifications input leakage current i il 25c vi ?1 +1 a power supply 1.8 v supply voltage (dvdd, avdd) full iv 1.7 1.8 1.9 v 1.8 v supply voltage noise limit dvdd full iv 64 mv rms avdd full iv 2 mv rms power-down current 25c iv 10 a transmitter total power de-interlacer off full vi 125 mw 1080p , typical random pattern with csc off de-interlacer on full vi 295 mw 1080i in, 1080p out, typical random pattern with csc off ac specifications tmds output clock frequency 25c iv 20 150 mhz tmds output clock duty cycle 25c iv 48 52 % input video clock frequency full iv 150 mhz input video data setup time t vsu full iv 1 ns input video data hold time t vhld full iv 0.7 ns tmds differential swing 25c vii 800 1000 1200 mv differential output timing low-to-high transition time 25c vii 75 175 ps high-to-low transition time 25c vii 75 175 ps vsync and hsync delay from de falling edge 25c iv 1 ui 2 vsync and hsync delay to de rising edge 25c iv 1 ui 2
adv7541 rev. a | page 4 of 12 parameter temp test level 1 min typ max unit test conditions/ comments audio ac timing 3 sclk duty cycle when n divide-by-2 is even full iv 40 50 60 % when n divide-by-2 is odd full iv 49 50 51 % i 2 s, s/pdif setup t asu full iv 2 ns i 2 s, s/pdif hold time t ahld full iv 2 ns lrclk setup time t asu full iv 2 ns lrclk hold time t ahld full iv 2 ns cec cecclk frequency 4 full viii 1 12 100 mhz cecclk accuracy full viii ?2 +2 % i 2 c interface scl clock frequency full iv 400 5 khz sda setup time t dsu full iv 100 ns sda hold time t dho full iv 100 ns setup for start t stasu full iv 0.6 s hold time for start t stah full iv 0.6 s setup for stop t stosu full iv 0.6 s bus free between stop and start t buf full iv 1.3 s scl high t high full iv 0.6 s scl low t low full iv 1.3 s 1 see section. explanation of test levels 2 ui = unit interval. 3 only applies to s/pdif if external mclk used. 4 12 mhz crystal for default register settings. 5 i 2 c data rates of 100 kh z and 400 khz supported.
adv7541 rev. a | page 5 of 12 absolute maximum ratings table 2. parameter rating digital inputs: i 2 c (ddcsda, ddcscl, sda, scl) and hpd +5.5 v to ?0.3 v digital inputs: video/audio inputs (cecio, cecclk) +3.63 v to ?0.3 v digital output current 20 ma operating temperature range ?40c to +100c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i. 100% production tested. ii. 100% production tested at 25c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c; guaranteed by design and characterization testing. vii. limits defined by hdmi specification ; guaranteed by design and characterization testing. viii. parameter is guaranteed by design. esd caution
adv7541 rev. a | page 6 of 12 pin configuration and fu nction descriptions adv7541 top view (ball side down) not to scale 08241-002 1 a b c d e f g 234 ball a1 corner 567 d3 d4 d6 d8 d10 d11 d12 d2 dvdd d5 d7 d9 d14 d13 d1 vsync gnd dvdd scl ddcsd a d15 d0 i2s hsync 1 de sclk 1 sda ddcsc l clk gnd lrclk hpd gnd cecclk cecio s/pdif 1 both hsync and sclk can be configured as mclk. avdd rext gnd avdd int tx2+ txc? txc+ tx0? tx0+ tx1? tx1+ tx2? figure 2. pin configuration table 3. pin function descriptions pin o. neonic tpe 1 description c7, b6, b7, a7, a6, a5, b5, a4, b4, a3, b3, a2, a1, b1, c1, d1 d[15:0] i video data input. digital input in rgb or ycbcr format. supports typical cmos logic levels from 1.8 v up to 3.3 v. e1 clk i video clock input. supports typical cmos logic levels from 1.8 v up to 3.3 v. d4 de i data enable bit for digital video. supports typical cmos logic levels from 1.8 v up to 3.3 v. c2 vsync i vertical sync input. supports typical cmos logic levels from 1.8 v up to 3.3 v. d3 hsync i horizontal sync input. supports typical cmos logic levels from 1.8 v to 3.3 v. f3 rext i sets internal reference currents. place 3.92 k resistor (1% tolerance) between this pin and ground. e4 hpd i hot plug detect signal. this indicates to the interface whether the receiver is connected. 1.8 v to 5.0 v cmos logic level. d2 i2s i i 2 s audio data inputs. these represent the two channels of audio available through i 2 s. supports typical cmos logic levels from 1.8 v up to 3.3 v. f1 s/pdif i s/pdif (sony/philips digital interface) audio input. this is the audio input from a sony/philips digital interface. supports typical cmos logic levels from 1.8 v up to 3.3 v. d5 sclk i i 2 s audio clock. supports typical cmos logic levels from 1.8 v up to 3.3 v. the sclk pin serves as mclk when configured with s/pdif. e3 lrclk i left/right channel selection. supports typical cmos logic levels from1.8 v up to 3.3 v. g1, g2 txc?/txc+ o differential clock output. differenti al clock output at pixel clock rate; tmds logic level. g7, f7 tx2?/tx2+ o differential output channel 2. di fferential output of the red data at 10 the pixel clock rate; tmds logic level. g5, g6 tx1?/tx1+ o differential output channel 1. differential o utput of the green data at 10 the pixel clock rate; tmds logic level. g3, g4 tx0?/tx0+ o differential output channel 0. differential o utput of the blue data at 10 the pixel clock rate; tmds logic level. f6 int o interrupt. cmos logic level. a 2 k pull-up resistor to interrupt the microcontroller i/o supply is recommended. f2, f5 avdd p 1.8 v power supply for tmds outputs. b2, c4 dvdd p 1.8 v power supply for digital and i/o power supply. these pins supply power to the digital logic and i/os. they should be filtered and as quiet as possible.
adv7541 rev. a | page 7 of 12 pin no. mnemonic type 1 description c3, e2, e5, f4 gnd p ground. the ground return for all circuitry on-chip. it is recommended that the adv7541 be assembled on a single, solid ground plane with careful attention given to ground current paths. d6 sda c serial port data i/o. this pin serves as the serial port data i/o slave for register access. supports cmos logic levels from 1.8 v to 3.3 v. c5 scl c serial port data clock. this pi n serves as the serial port data clock slave for register access. supports cmos logic levels from 1.8 v to 3.3 v. c6 ddcsda c serial port data i/o to receiver. this pin se rves as the master to the ddc bus. 5 v cmos logic level. d7 ddcscl c serial port data clock to receiver. this pin se rves as the master clock for the ddc bus. 5 v cmos logic level. e7 cecio c cec i/o. e6 cecclk c cec external clock. can be from 1 mhz to 100 mhz. 1 i = input, o = output, p = power supply, and c = control.
adv7541 rev. a | page 8 of 12 applications information design resources analog devices, inc., offers the following design resources: ? evaluation kits ? reference design schematics ? hardware and software guides ? software driver reference code ? hdmi compliance pretest services ? other support documentation is available under the nondisclosure agreement (nda) from atv_videotx_apps@analog.com. other references include the following: eia/cea-861e , which describes audio and video infoframes as well as the e-edid structure for hdmi. it is available from consumer electronics association (cea). the hdmi v.1.4, a defining document for hdmi version 1.4, and the hdmi compliance test specification version 1.4 are available from hdmi licensing, llc.
adv7541 rev. a | page 9 of 12 outline dimensions 111908-a a b c d e f g 0.380 0.355 0.330 3.750 3.700 sq 3.650 1 2 3 45 bottom view (ball side up) top view (ball side down) 3.00 ref sq ball a1 identifier seating plane 6 7 coplanarity 0.03 0.50 ball pitch 0.650 0.595 0.540 0.340 0.320 0.300 0.270 0.240 0.210 figure 3. 49-ball wafer level chip scale package [wlcsp] (cb-49-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADV7541BCBZ-2RL ?25c to +85c 49-ball wafer level chip scale package [wlcsp] with hdcp keys cb-49-2 adv7541bcbz-p-2rl ?25c to +85c 49-ball wafer level chip scale package [wlcsp] with no hdcp keys cb-49-2 eval-adv7541-ckz evaluation kit (with hdcp keys) eval-adv7541p-ckz evaluation kit (with no hdcp keys) 1 z = rohs compliant part.
adv7541 rev. a | page 10 of 12 notes
adv7541 rev. a | page 11 of 12 notes
adv7541 rev. a | page 12 of 12 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2009-2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08241-0-6/10(a)

▲Up To Search▲

Price & Availability of ADV7541BCBZ-2RL

	To Download ADV7541BCBZ-2RL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .